Multipliers can be implemented in programmable logic devices implementing logic, memory or a combination thereof. Multipliers can be implemented in a memory using a look-up-table (LUT). The contents of the LUT, when implemented for a multiplier, are typically written when the device is programmed and are not changed. Recently, programmable logic devices with multiple port memories have become available. The multiple port memories allow a user to perform multiple reads from the same memory in parallel.
Conventional approaches for providing programmable logic multipliers in a memory implement a single port memory, containing a look-up table (LUT) of results. The results are partial products of addresses input to the memory. For each LUT, one partial product can be generated per clock cycle. If a user desires to generate multiple partial products per clock cycle (i.e., typical of fast multipliers), the user must implement multiple LUTs (therefore multiple programmable devices). The multiple LUTs require additional memory resources including area.
Conventional approaches can only read one partial product per LUT, per clock cycle. To provide fast multipliers in conventional approaches, several LUTs must be implemented in parallel. Furthermore, conventional approaches require additional device resources.